#
# Bcm7038 events
#
# As standard the CPU supports 2 performance counters.  Event 0, 2, 3, 4
# are available on both counters; events 11, 12, 13, 14-counter1 are reserved;
# Event 15-counter1 and event 1-counter0 are the same;
# the remaining are counter-specific.

event:0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor cycles (PClock)
event:2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Load, prefetch/CacheOps execution (no sync)
event:3 counters:0,1 um:zero minimum:500 name:STORES : Store execution
event:4 counters:0,1 um:zero minimum:500 name:BRANCHES : Branch execution (no jumps or jump registers)

#
# Events specific to counter 0
#
event:1 counters:0 um:zero minimum:500 name:INSTRUCTIONS_FETCHED : Instructions fetched
event:5 counters:0 um:zero minimum:500 name:FAILED_CONDITIONAL_STORES : Failed conditional stores
event:6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : Data micro-TLB accesses
event:7 counters:0 um:zero minimum:500 name:ITLB_MISS : ITLB misses
event:8 counters:0 um:zero minimum:500 name:DTLB_MISS : DTLB miss
event:9 counters:0 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses (no D-cache misses)
event:10 counters:0 um:zero minimum:500 name:INSTRUCTION_SCHEDULED : Instruction scheduled
event:14 counters:0 um:zero minimum:500 name:DUAL_INSNS_EXECUTED : Dual issued  instructions executed
event:15 counters:0 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : Instructions executed

#
# Events specific to counter 1
#
event:1 counters:1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : Instructions executed
event:5 counters:1 um:zero minimum:500 name:FP_INSTRUCTIONS : FP instruction execution
event:6 counters:1 um:zero minimum:500 name:DCACHE_LINE_EVICTED : Data cache line evicted
event:7 counters:1 um:zero minimum:500 name:TLB_MISS : TLB miss exceptions
event:8 counters:1 um:zero minimum:500 name:BRANCH_MISPREDICTED : Branch mispredicted
event:9 counters:1 um:zero minimum:500 name:DATA_CACHE_MISS : Data cache miss
event:10 counters:1 um:zero minimum:500 name:STALLS : Instruction stall in M stage due to scheduling conflicts
event:15 counters:1 um:zero minimum:500 name:COP2_INSTRUCTIONS_EXECUTED : COP2 instructions executed
